A memory includes an oscillator for generating a self-refresh request signal. Unfortunately, the oscillator has a variation in oscillation period due to process variations. Disadvantageously, required refresh time varies from semiconductor chip to another. To overcome the disadvantage, the frequency division number for a refresh request signal is changed in each semiconductor chip in a probing test. Accordingly, the period of the refresh request signal is adjusted to reduce a variation in required period of the refresh request signal between semiconductor chips.
The memory includes normal memory cells and redundant memory cells. A problem which arises in this case is the relation between a first probing test before replacing a normal memory cell with a redundant memory cell (hereinafter, “before redundancy”) and a second probing test after replacing a normal memory cell with a redundancy memory cell (hereinafter, “after redundancy”). In the first probing test before redundancy, it is necessary to set the period of the refresh request signal before redundancy to be longer than that after redundancy in order to prevent a failure that is caused by an insufficient refresh operation in the second probing test after redundancy. However, it is difficult to set the period of the refresh request signal before redundancy to be longer than that after redundancy using an appropriate margin for each semiconductor chip, since it is impossible to get the frequency division number, which differs from semiconductor chip to another, from outside.
Japanese Laid-open Patent Publication No. 2001-184860 discloses a semiconductor memory device having a self-refresh mode. The semiconductor memory device includes self-refresh term varying means that receives a predetermined external address signal, generates an oscillation period control signal on the basis of the predetermined external address signal, and varies the oscillation period of an oscillation circuit in accordance with the oscillation period control signal to vary the self-refresh term.
Japanese Laid-open Patent Publication No. 2006-4557 discloses a semiconductor memory device including the following elements. A memory array includes a plurality of memory cells each of which needs a refresh operation in order to hold data. A first control circuit writes predetermined data into predetermined memory cells (referred to as monitor cells) in the memory array. A second control circuit reads data from the monitor cells, in which the predetermined data has been written, after a lapse of time equal to a refresh period or a lapse of predetermined time shorter than the refresh period. A third control circuit compares the data read from the monitor cells with the predetermined data to measure an error count or error rate and variably controls the refresh period on the basis of the measured error count or error rate.